Moore’s Law has always been a mystical but achievable mantra in the semiconductor world. But a development at HP Labs could outpace Moore’s Law by more than three times! We take a closer look at HP’s new field programmable nanowire interconnect.

In January 2007, HP announced the findings of its ongoing research that could result in chips eight times denser than today’s versions. This, in a way, signifies HP’s out-pacing the predictions of Moore’s Law, an observation made in 1965 by Gordon Moore of Intel to the effect that every 18 months, the number of transistors that could be packed into a chip would double. This was achieved mainly by reducing the size of transistors. However, researchers felt that this could not apply beyond an extent, as packing more and smaller transistors closely into chips would lead to high energy dissipation, heating, consumption and so on… simple physics.

So, when the laws of physics and that of Moore’s cross swords, which will win? Well, perhaps HP. The company’s recent research has opened up the possibility of creating field programmable gate arrays (FPGAs) up to eight times denser than the current generation, using the same transistor size, and also consuming less energy per computation.

Field programmable gate arrays are chips that can be adapted for specific end-user applications, as these integrated circuits are made with programmable logic components and interconnects. They are used widely in industries such as communications and consumer electronics. Therefore, denser FPGAs would mean more power to these industries – hence the buzz around HP’s announcement.

Under the FPNI hood

According to HP, eight times denser FPGAs are possible thanks to an architecture it developed called field programmable nanowire interconnect (FPNI). This is a variation of normal FPGA technology and has a nanoscale crossbar switch structure layered on top of conventional CMOS (complementary metal oxide semiconductors). Here, all logic operations are performed in the CMOS, while the signal routing in the circuit is done by a crossbar placed above the transistor layer. In conventional FPGAs, around 80-90 per cent of the CMOS is used for signal routing. Since that is removed to the crossbar layer in this technology, the circuit is much more efficient with a higher density of transistors being available for performing logic operations. The electrical power required for signal routing is also much lesser.

As explained by Stan Williams of HP Labs in an official press release: “As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics. Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”

The research is in the simulation stage now, but HP hopes to have a lab prototype ready within a year. Manufacturing of actual chips using this approach should not be difficult, according to HP, since the same transistor size is used, enabling current generation manufacturing techniques and infrastructure to be used, with slight modifications. Don’t let your hopes rise too high though, because the technology is expected to be commercially available only in 2010 and, that too, using only 15-nanometre-wide crossbar wires. Smaller 4.5-nanometre-wide wires are expected to be available around 2020.

Moore continues to buzz

In a technical paper titled “Nano/CMOS Architectures Using Field-Programmable Nanowire Interconnect” describing the technology, HP Labs researchers Greg Snider and Stan Williams wrote: “Placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance and can be used to significantly extend Moore’s Law without having to shrink the transistors.”

(The complete research paper can be found at www.iop.org/journals/nano, while the press release can be found at http://www.hp.com/hpinfo/newsroom/press/2007/070116a.html)
If HP succeeds in fabricating this chip, it would mean skipping three ‘Moore generations.’ Not surprisingly, the media has been more interested about the possible outpacing of Moore’s Law than about the actual technology developed by HP. But some level-headed scientists feel this is more hype than breakthrough.

In fact, Gordon Haff, a chip analyst and principal IT advisor at Illuminata, cut through the Moore’s Law hype in Red Herring, saying: “Moore’s Law is essentially an observation about the rate of increasing density in processor technology and processor design, so it’s not an absolute law in any sense. A variety of techniques have been used over the past decades to essentially increase transistor density at a rate that is often called Moore’s Law. It’s a number that has varied a bit up and down over the years but has been relatively constant. There is a constant ongoing advance to increase transistor density coming from any number of people.”

Law? What law?: Experts speak

Professor M. Balakrishnan of the department of computer science and engineering, IIT-Delhi, sides with Haff in playing down the Moore’s Law hype, saying that it is not an absolute law of physics, just a visionary statement on the trend microelectronics would follow. His comments on the technology itself, based on what he considers inadequate information in the press release, are to the effect that using the FPGA transistor size would simply not make the device smaller or the density higher. You would get the same density as those of FPGAs. “If programmable interconnects are being used (on a different layer), details have to be seen to find out how it is still faster and cooler. Also, FPGAs compare unfavourably both in power and performance at present. It is their cost of production in low volumes that makes them an attractive technology option,” he adds.

Dr Srinivas Katkoori, associate professor, CSE department, University of South Florida, Tampa, USA, too agrees wholeheartedly with Haff’s observation that Moore's Law is not a law of physics. “The semiconductor industry uses Moore's Law more as a marketing tool than anything else. While Gordon Moore of Intel has empirically found a relationship that states that the transistor density doubles every 18 months or so, there is no reason why we should stick to this rate nor should we bend our backs to satisfy this ‘law’,” says Katkoori. “Instead we should try to push the technology limit to pack as many transistors as possible in the same chip area; thus the rate could be double, triple, quadruple, or whatever factor that the technology entails.”

And more hype…about nanotechnology

Another term that seems to be much in vogue today is ‘nanotechnology’ and, obviously, that is another portion of HP’s press release that the media is feeding on. Haff, who seems to have been on a bubble-bursting spree, has commented in the Red Herring report: “At some level, everything in modern processor development is nanotechnology by some definition, and all modern processor technology is CMOS technology at the nanometre scale.”

According to Katkoori, as of today, the CMOS technology node is in nanometres (70nm and below) and purely going by the scale of its dimensions—nanometres—it can be referred to as ‘nanotechnology’. But the usage of the word ‘nanotechnology’ as intended by Richard Feynman is to work at the nanoscale of matter to realise computing elements. Carbon nanotubes seem to be a promising technology and falls into this interpretation
of nanotechnology. However, carbon nanotube development is still in a nascent stage.

“From my understanding of the state-of-the-art of the carbon nanotube technology, arrived at through personal communication with colleagues working actively in this field, I learnt that there are mainly two roadblocks: lack of repeatability of nanotubes and the inability to precisely control nanotube arrays. Both these roadblocks come in the way of the mass manufacturing of nanosystems,” says Katkoori. “From reading the press coverage about HP’s new technology, it looks like HP is combining CMOS technology (transistors) and nanotechnology (interconnect) to realise a hybrid technology.”

“While I do not completely know the details of the technology underlying HP's claim, in principle, it should be possible for nanowires to replace the traditional metal-based interconnect fabric and thus facilitate much higher transistor density. If this is indeed possible, then it a great breakthrough, in which case we need not restrict it to FPGA technology. FPGAs traditionally have lower transistor density as well as speed than that of dedicated ASICs (Application Specific ICs). If HP's claim is indeed true, then they must have succeeded in overcoming the above two roadblocks… did they?” questions Katkoori.

We’ll have to wait for HP to be more forthcoming with details on this. Till then, well, speculation it shall be!